Design Techniques of Energy Efficient PLL for Enhanced Noise and Lock Performance

Phase locked loops(PLLs)are vital building blocks of communication sys-tems whose performance dictates the quality of communication.The design of PLL to o_er superior performance is the prime objective of this research.It is desirable for the PLL to have fast locking,low noise,low reference spur,wide lock range,low power consumption consuming less silicon area.To achieve these performance parameters simultaneously in a PLL being a challenging task is taken up as a scope of the present work.A comprehensive study of the performance linked PLL components along with their design challenges is made in this report.The phase noise which is directly related to the dead zone of the PLL is minimized using an e_cient phase frequency detector(PFD)in this thesis.Here a voltage variable delay element is inserted in the reset path of the PFD to reduce the dead zone.An adaptive PFD architecture is also proposed to have a low noise and fast PLL simultaneously.In this work,before locking a fast PFD and in the locked state a low noise PFD operates to dictate the phase di_erence of the reference and feedback signals.To reduce the reference spur,a novel charge pump architecture is proposed which eventually reduces the lock time up to a great extent.In this charge pump a single current source is employed to reduce the output current mis-match and transmission gates are used to reduce the non ideal e_ects.Besides this,the fabrication process variations have a predominant e_ect on the PLL performance,which is directly linked to the locking capability.This necessitates a manufacturing process variation tolerant design of the PLL.In this work an e_cient multi-objective optimization method is also applied to at-tain multiple optimal performance objectives.The major performances under consideration are lock time,phase noise,lock range and power consumption

Design of an Application Specific Instruction Set Processor Using LISA

A Digital Signal Processor with specific instruction sets and meant for a specific application is called as Application Specific Instruction set Processor(ASIP). To design an ASIP many approaches are available. However optimization of an ASIP becomes handy if it is designed in a higher level of abstraction that is higher than Register Transfer Level (RTL). Application Description Languages (ADLs) are becoming popular recently because of its quick and optimal design convergence achievement capability during the design of ASIPs. Several stages are required to design a processor which are architecture design implementation, software development, instruction and system verification. Verification of such ASIPs at various design stages is a tedious job to do. This thesis presents the architecture description of a simple DSP processor using ADL based instruction set description. The design process is more consistent after allowing maximum flexibility here. Further more, it enables the design process in both instruction and cycle accurate modes. The design process of a three stage pipelined FIR Filter processor is demonstrated as a case study. Further optimization can be done with respect to resources, memory size and power consumption by changing the LISA code written in CoWare platform

Розширене дослідження позиційно-залежного багатоканального GAA MOSFET та його впливу на характеристики пристрою

У роботі проведено симуляційне дослідження багатоканального польового транзистора з горизонтальним розташуванням каналів та круговим затвором (GAA MOSFET) з розрахунком розділення каналів. Моделювання виконується у низько-технологічних вузлах з урахуванням квантового ефекту. Ізолятор, який використовується в розглянутій моделі, є high-k діелектриком, що дозволяє зменшити масштаб пристрою. Детально досліджуються розділення кремнієвих каналів та його вплив на характеристики пристрою. Отримані таким чином характеристики, а саме струм стоку (ID), порогова напруга (Vth), крутизна (gm) та коефіцієнт перемикання (Ion/Ioff), порівнюються для різних розділень каналів. Крім того, детально вивчається струм витоку та пов'язаний з ним короткоканальний ефект, такий як підпорогове коливання (SS), та його залежність від розділення каналів. Покращене на 28,9 % значення струму включення при SS, рівному 70,34 мВ/дек, досягається для розділення каналів в 10 нм. Однак коефіцієнт перемикання 9,13e+08 отримано для розділення в 6 нм, що порівняно вище, ніж для розділення в 9 і 10 нм.In this paper, a simulation study is carried out for a multi-channel gate all around (GAA) MOSFET with channel separation calculation. The simulation is performed in lower technology nodes by taking the quantum effect into consideration. The insulator used in this model is a high-k dielectric, which allows the device to be scaled down. The separation between the silicon channel and its effect on device performance is investigated extensively. The performance thus obtained is compared with different channel separations in terms of drain current (ID), threshold voltage (Vth), transconductance (gm) and switching ratio (Ion/Ioff). Further, the leakage current and associated short channel effect such as subthreshold swing (SS) and its dependence on channel separation are studied in detail. An improved value of on-current of 28.9 % along with SS of 70.34 mV/dec is achieved for a separation of 10 nm. However, a switching ratio of 9.13e+08 is obtained for a separation of 6 nm which is comparatively higher than 9 and 10 nm separation

Dead Zone Minimization Using Variable-Delay Element in CP-PLL for 5G Applications

The deadzone occurring in a phase-frequency detector (PFD) is a critical parameter that affects the performance of a phase-locked loop (PLL). Though a fixed-delay element reduces the deadzone, it creates an imbalance in the pulse-arrival time and among the up and down signals to the charge pump, which increases the phase noise in the output spectrum of the PLL. Therefore, in this work a new variable-delay element (VDE) is incorporated in the PFD to reduce the dead zone and consequently the phase noise of the PLL. The performance of the proposed PFD incorporated in PLL is analyzed using cadence virtuoso 90 nm CMOS technology, achieving a phase noise of −148.89 dBc/Hz at a frequency offset of 1 MHz, a lock time of 6.01 us, a power of 0.056 mW, and a dead zone of 110.5 ps, while operating at 3.5 GHz of frequency, making it suitable for 5G applications

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